*triac

Waiting for data

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x10

x0.1

Sheet:1

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SPICE

SPICE Netlist

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** triac **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: D1
xD1 9 6 0 MAC08MT1/ON_D1

* Component: D2
dD2 7 6 DIODE_D2 AREA=1

* Component: R1
rR1 3 2 99000 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 0 3 1000 VIRTUAL_RESISTANCE_R2

* Component: U1
xU1 1 3 2 3T_VIRTUAL_U1 PARAMS: VOS=0 IBS=0 IOS=0 AVOL=200000 BW=100000000 RI=10000000 RO=10 VOMP=12 VOMN=-12

* Component: U2
xU2 2 11 5 4 7 5T_VIRTUAL_U2 PARAMS: VOS=0.001 IBS=8e-8 IOS=2e-8 AVOL=200000 BW=100000000 SR=1000000 CMRR=100 ISC=0.025 RI=10000000 RO=10

* Component: V1
vV1 1 0 dc 0.0027 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V2
vV2 5 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V3
vV3 0 4 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V4
vV4 11 0 dc 0.2652 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V5
vV5 9 10 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 {120*1.414213562} 60 0 0 0 )

* Component: X1
xX1 10 0 VIR_LAMP_X1

* --- Circuit Models ---

* D2 model
.model DIODE_D2 D( IS=1e-14 RS=0 N=1 BV=1e+30
+ TT=0 CJO=0 VJ=1 M=0.5 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 IBV=1e-10
+ IBVL=0 IKF=1e+30 ISR=0 NBV=1 NBVL=1 NR=2 TBV1=0 TBV2=0 TIKF=0
+ TRS1=0 TRS2=0
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* --- Subcircuits ---

* D1 subcircuit
.subckt MAC08MT1/ON_D1 MT2 gate MT1 PARAMS:
+ Vdrm=600v Idrm=10u
+ Ih=5ma dVdt=10e6
+ Igt=10ma Vgt=2.0v
+ Vtm=1.9v Itm=1.1
+ Ton=1.5u
* Where:
* Vdrm => Forward breakover voltage
* Idrm => Peak blocking current
* Ih => Holding current [MT2(+)]
* dVdt => Critical value for dV/dt triggering
* Igt => Gate trigger current [MT2(+),G(-)]
* Vgt => Gate trigger voltage [MT2(+),G(-)]
* Vtm => On-state voltage
* Itm => On-state current
* Ton => Turn-on time
* Main conduction path
Striac MT2 MT20 cntrol 0 Vswitch ; controlled switch
Dak1 MT20 MT22 Dak OFF ; triac is initially off
VIak MT22 MT1 ; current sensor
Striacr MT2 MT23 cntrolr 0 Vswitch ; controlled switch
Dka1 MT21 MT23 Dak OFF ; triac is initially off
VIka MT1 MT21 ; reverse current sense
* dVdt Turn-on
Emon dvdt0 0 TABLE {ABS(V(MT2,MT1))} (0 0) (2000 2000)
CdVdt dvdt0 dvdt1 100pfd ; displacement current
Rdlay dvdt1 dvdt2 1k
VdVdt dvdt2 MT1 DC 0.0
EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
RdVdt condvdt 0 1meg
* Gate
Rseries gate gate1 {(Vgt-0.65)/Igt}
Rshunt gate1 gate2 {0.65/Igt}
Dgkf gate1 gate2 Dgk
Dgkr gate2 gate1 Dgk
VIgf gate2 MT1 DC 0.0 ; current sensor
* Gate Turn-on
Egate congate 0 TABLE {(ABS(i(VIgf))-0.95*Igt)} (0 0) (1m 10)
Rgate congate 0 1meg
* Holding current, holding voltage (Quadrant I)
Emain1 main1 0 TABLE {i(VIak)-Ih+5e-3*i(VIgf)/Igt} (0 0) (.1m 1)
Rmain1 main1 0 1meg
Emain2 main2 0 TABLE {v(MT2,MT1)-(Ih*Vtm/Itm)} (0 0) (.1m 1)
Rmain2 main2 0 1meg
Emain3 cnhold 0 TABLE {v(main1,0)*v(main2,0)} (0 0) (1 10)
Rmain3 cnhold 0 1meg
* Holding current, holding voltage (Quadrant III)
Emain1r main1r 0 TABLE {i(VIka)-Ih-5e-3*i(VIgf)/Igt} (0 0) (.1m 1)
Rmain1r main1r 0 1meg
Emain2r main2r 0 TABLE {v(MT1,MT2)-(Ih*Vtm/Itm)} (0 0) (.1m 1)
Rmain2r main2r 0 1meg
Emain3r cnholdr 0 TABLE {v(main1r,0)*v(main2r,0)} (0 0) (1 10)
Rmain3r cnholdr 0 1meg
* Main
Emain4 main4 0 table {(1.0-ABS(i(VIgf))/Igt)} (0 0) (1 1)
Rmain4 main4 0 1meg
Emain5 cnmain 0 table {v(mt2,mt1)-1.05*Vdrm*v(main4)} (0 0) (1 10)
Rmain5 cnmain 0 1meg
Emain5r cnmainr 0 table {v(mt1,mt2)-1.05*Vdrm*v(main4)} (0 0) (1 10)
Rmain5r cnmainr 0 1meg
* Turn-on/Turn-off control (Quadrant I )
Eonoff contot 0 TABLE
+ {v(cnmain)+v(congate)+v(cnhold)+v(condvdt)} (0 0) (10 10)
* Turn-on/Turn-off delays (Quadrant I)
Rton contot dlay1 825
Dton dlay1 cntrol Delay
Rtoff contot dlay2 {2.9E-3/Ton}
Dtoff cntrol dlay2 Delay
Cton cntrol 0 {Ton/454}
* Turn-on/Turn-off control (Quadrant III)
Eonoffr contotr 0 TABLE
+ {v(cnmainr)+v(congate)+v(cnholdr)+v(condvdt)} (0 0) (10 10)
* Turn-on/Turn-off delays (Quadrant III)
Rtonr contotr dlayr1 825
Dtonr dlayr1 cntrolr Delay
Rtoffr contotr dlayr2 {2.9E-3/Ton}
Dtoffr cntrolr dlayr2 Delay
Ctonr cntrolr 0 {Ton/454}
* Controlled switch model
.MODEL Vswitch vswitch
+ (Ron = {(Vtm-0.7)/Itm}, Roff = {1.75E-3*Vdrm/Idrm},
+ Von = 5.0, Voff = 1.5)
* Diodes
.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL Dak D (Is=4E-11 Cjo=5pf)
* Allow the gate to float if required
Rfloat gate MT1 1e10
.ends

* U1 subcircuit
.SUBCKT 3T_VIRTUAL_U1 in_pos in_neg out PARAMS: AVOL=500k BW=10Meg RI=10Meg RO=0 VOS=0 IBS=0 IOS=0 VOMP=15 VOMN=-15

* Input Stage: Rin, Ibias, Voffset
VOS in_pos 4 {VOS}
Ibias1 4 0 {IBS}
Ibias2 in_neg 0 {IBS}
Ios 4 in_neg {IOS/2}
Rin 4 in_neg {RI}

*Middle stage: Gain, frequency, voltage limiting
Bgain 0 6 I={v(4,in_neg)*AVOL/1meg }
R1 6 0 1meg
CP1 6 0 {AVOL/(2*pi*1meg*BW)}

Vpos 9 0 {VOMP}
Dlimit_pos 6 9 d1

Vneg 10 0 {VOMN}
Dlimit_neg 10 6 d1

.model d1 d(n=0.1)

*Output stage: Buffer, output resistance
E2 7 0 6 0 1
Rout 7 out {RO}
.ends

* U2 subcircuit
.subckt 5T_VIRTUAL_U2 In_p In_n Vpos Vneg Out params: AVOL=200k BW=20Meg CMRR=100
+SR=1Meg RO=75 ISC=25m RI=100meg VOS=0.1m IBS=1n IOS=1p
.param Rp1=1e6
.param Rs1=1e6
.param K_Is2a=sqrt(AVOL)/Rs1
.param K_Is2b=sqrt(AVOL)/Rp1
.param Cp1={AVOL/(2*pi*BW*Rp1)}
.param CMRR_lin=10**(CMRR/20)

Rin In_p In_n {RI}
Bcm 4 3 V = { V(cm)/CMRR_lin}
Voff In_p 4 {VOS}
Ibias1 In_p 0 {IBS}
Ibias2 In_n 0 {IBS}
Ioffset In_p In_n {IOS/2}

Rcm1 In_p cm 10meg
Rcm2 In_n cm 10meg

BIs1a vref vs2a I = { K_Is2a*(V(3)-V(In_n)) }
Rs1 vs2a vref {Rs1}

BIs2b vref vs2b I = { K_Is2b*(V(vs2a)-v(vref)) }
Rp1 vs2b vref {Rp1}
VCp1sense vs2b vs2b_ 0
Cp1 vs2b_ vref {Cp1}

D3 vs2b_ 8 Limit_Diode
D4 8 vpos Limit_Diode
B_SRp 8 vpos I={I(VCp1sense)- (Cp1*SR)}

D5 10 vs2b_ Limit_Diode
D6 Vneg 10 Limit_Diode
B_SRn Vneg 10 I={-1*I(VCp1sense)-(Cp1*SR)}

DVpclip vs2b_ Vpos V_limit
DVnclip Vneg vs2b_ V_limit

Bout vref out_ I={(V(vs2b)-v(vref))/RO}
Rout vref out_ {RO}
Voutsense out_ out 0

D9 out 15 Limit_Diode
D10 15 vpos Limit_Diode
B_outp 15 vpos I={I(Voutsense)- ISC}

D11 16 out Limit_Diode
D12 vneg 16 Limit_Diode
B_outn vneg 16 I={-1*I(Voutsense)-ISC}

R5 Vpos mid 1000000
R6 mid Vneg 1000000
Eref vref 0 mid 0 1

.MODEL Limit_Diode D (IS= 1.0e-12)
.MODEL V_limit D(n=0.1)
.ends

* X1 subcircuit
.subckt VIR_LAMP_X1 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {127^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 220 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 127, {abs(V(port1, port2)) / 127}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 127}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

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Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

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Minimum output voltage level to produce a high signal.

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Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

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Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Name triac

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RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

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Temp

℃

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Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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triac