*diac triac

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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triac

circuito eletricidade

diac

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SPICE

SPICE Netlist

This is a text-based representation of the circuit.
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Probes do not appear in netlists.

** diac triac **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C2
cC2 5 0 5e-8

* Component: D1
xD1 2 5 MKP3V240/ON_D1

* Component: D2
xD2 3 2 0 MAC08MT1/ON_D2

* Component: R1
rR1 8 1 2000 VIRTUAL_RESISTANCE_R1

* Component: R2
xR2 5 8 8 Potentiometer_R2 PARAMS: res=45500 posPercent=45

* Component: V1
vV1 1 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 220 60 0 0 0 )

* Component: X1
xX1 1 3 VIR_LAMP_X1

* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* --- Subcircuits ---

* D1 subcircuit
**************************************
* Model Generated by SCD Eval Lab *
* July 10, 2002 *
* Copyright(c) On Semiconductor *
* All Rights Reserved *
*Commercial Use or Resale Restricted *
**************************************
*$
.subckt MKP3V240/ON_D1 MT1 MT2
X1 MT1 MT2 MT2 SCR_MKP3V240
X2 MT2 MT1 MT1 SCR_MKP3V240
*$
*
.SUBCKT SCR_MKP3V240 anode gate cathode PARAMS:
*SCR
*MODEL FORMAT: PSpice
+ Vdrm=180v Vrrm=400v Idrm=1u
+ Ih=10ma dVdt=10e6
+ Igt=25ua Vgt=0.8v
+ Vtm=1.1v Itm=1.0
+ Ton=2u Toff=15u

* Where:
* Vdrm => Forward breakover voltage
* Vrrm => Reverse breakdown voltage
* Idrm => Peak blocking current
* Ih => Holding current
* dVdt => Critical value for dV/dt triggering
* Igt => Gate trigger current
* Vgt => Gate trigger voltage
* Vtm => On-state voltage
* Itm => On-state current
* Ton => Turn-on time
* Toff => Turn-off time

* Main conduction path
Scr anode anode0 control 0 Vswitch ; controlled switch
Dak1 anode0 anode2 Dakfwd OFF ; SCR is initially off
Dka cathode anode0 Dkarev OFF
VIak anode2 cathode ; current sensor

* dVdt Turn-on
Emon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000)
CdVdt dvdt0 dvdt1 100pfd ; displacement current
Rdlay dvdt1 dvdt2 1k
VdVdt dvdt2 cathode DC 0.0
EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
RdVdt condvdt 0 1meg

* Gate
Rseries gate gate1 {(Vgt-0.65)/Igt}
Rshunt gate1 gate2 {0.65/Igt}
Dgkf gate1 gate2 Dgk
VIgf gate2 cathode ; current sensor

* Gate Turn-on
Egate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10)
Rgate1 gate4 0 1meg
Egon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10)
Rgon1 congate 0 1meg

* Main Turn-on
EItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000)
RItot Itot 0 1meg
Eprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1)
Rprod prod 0 1meg
Elin conmain 0 TABLE
+ {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10)
Rlin conmain 0 1meg

* Turn-on/Turn-off control
Eonoff contot 0 TABLE
+ {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10)

* Turn-on/Turn-off delays
Rton contot dlay1 825
Dton dlay1 control Delay
Rtoff contot dlay2 {290*Toff/Ton}
Dtoff control dlay2 Delay
Cton control 0 {Ton/454}

* Reverse breakdown
Dbreak anode break1 Dbreak
Dbreak2 cathode break1 Dseries

* Controlled switch model
.MODEL Vswitch vswitch
+ (Ron = {(Vtm-0.7)/Itm}, Roff = {Vdrm*Vdrm/(Vtm*Ih)},
+ Von = 5.0, Voff = 1.5)

* Diodes
.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL Dseries D (Is=1E-14)
.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01)
.MODEL Dakfwd D (Is=4E-11 Cjo=5pf)
.MODEL Dbreak D (Ibv=1E-7 Bv={1.1*Vrrm} Cjo=5pf Rs=0.5)

* Allow the gate to float if required
Rfloat gate cathode 1e10

.ENDS
.ENDS MKP3V240/ON
*$

* D2 subcircuit
.subckt MAC08MT1/ON_D2 MT2 gate MT1 PARAMS:
+ Vdrm=600v Idrm=10u
+ Ih=5ma dVdt=10e6
+ Igt=10ma Vgt=2.0v
+ Vtm=1.9v Itm=1.1
+ Ton=1.5u
* Where:
* Vdrm => Forward breakover voltage
* Idrm => Peak blocking current
* Ih => Holding current [MT2(+)]
* dVdt => Critical value for dV/dt triggering
* Igt => Gate trigger current [MT2(+),G(-)]
* Vgt => Gate trigger voltage [MT2(+),G(-)]
* Vtm => On-state voltage
* Itm => On-state current
* Ton => Turn-on time
* Main conduction path
Striac MT2 MT20 cntrol 0 Vswitch ; controlled switch
Dak1 MT20 MT22 Dak OFF ; triac is initially off
VIak MT22 MT1 ; current sensor
Striacr MT2 MT23 cntrolr 0 Vswitch ; controlled switch
Dka1 MT21 MT23 Dak OFF ; triac is initially off
VIka MT1 MT21 ; reverse current sense
* dVdt Turn-on
Emon dvdt0 0 TABLE {ABS(V(MT2,MT1))} (0 0) (2000 2000)
CdVdt dvdt0 dvdt1 100pfd ; displacement current
Rdlay dvdt1 dvdt2 1k
VdVdt dvdt2 MT1 DC 0.0
EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
RdVdt condvdt 0 1meg
* Gate
Rseries gate gate1 {(Vgt-0.65)/Igt}
Rshunt gate1 gate2 {0.65/Igt}
Dgkf gate1 gate2 Dgk
Dgkr gate2 gate1 Dgk
VIgf gate2 MT1 DC 0.0 ; current sensor
* Gate Turn-on
Egate congate 0 TABLE {(ABS(i(VIgf))-0.95*Igt)} (0 0) (1m 10)
Rgate congate 0 1meg
* Holding current, holding voltage (Quadrant I)
Emain1 main1 0 TABLE {i(VIak)-Ih+5e-3*i(VIgf)/Igt} (0 0) (.1m 1)
Rmain1 main1 0 1meg
Emain2 main2 0 TABLE {v(MT2,MT1)-(Ih*Vtm/Itm)} (0 0) (.1m 1)
Rmain2 main2 0 1meg
Emain3 cnhold 0 TABLE {v(main1,0)*v(main2,0)} (0 0) (1 10)
Rmain3 cnhold 0 1meg
* Holding current, holding voltage (Quadrant III)
Emain1r main1r 0 TABLE {i(VIka)-Ih-5e-3*i(VIgf)/Igt} (0 0) (.1m 1)
Rmain1r main1r 0 1meg
Emain2r main2r 0 TABLE {v(MT1,MT2)-(Ih*Vtm/Itm)} (0 0) (.1m 1)
Rmain2r main2r 0 1meg
Emain3r cnholdr 0 TABLE {v(main1r,0)*v(main2r,0)} (0 0) (1 10)
Rmain3r cnholdr 0 1meg
* Main
Emain4 main4 0 table {(1.0-ABS(i(VIgf))/Igt)} (0 0) (1 1)
Rmain4 main4 0 1meg
Emain5 cnmain 0 table {v(mt2,mt1)-1.05*Vdrm*v(main4)} (0 0) (1 10)
Rmain5 cnmain 0 1meg
Emain5r cnmainr 0 table {v(mt1,mt2)-1.05*Vdrm*v(main4)} (0 0) (1 10)
Rmain5r cnmainr 0 1meg
* Turn-on/Turn-off control (Quadrant I )
Eonoff contot 0 TABLE
+ {v(cnmain)+v(congate)+v(cnhold)+v(condvdt)} (0 0) (10 10)
* Turn-on/Turn-off delays (Quadrant I)
Rton contot dlay1 825
Dton dlay1 cntrol Delay
Rtoff contot dlay2 {2.9E-3/Ton}
Dtoff cntrol dlay2 Delay
Cton cntrol 0 {Ton/454}
* Turn-on/Turn-off control (Quadrant III)
Eonoffr contotr 0 TABLE
+ {v(cnmainr)+v(congate)+v(cnholdr)+v(condvdt)} (0 0) (10 10)
* Turn-on/Turn-off delays (Quadrant III)
Rtonr contotr dlayr1 825
Dtonr dlayr1 cntrolr Delay
Rtoffr contotr dlayr2 {2.9E-3/Ton}
Dtoffr cntrolr dlayr2 Delay
Ctonr cntrolr 0 {Ton/454}
* Controlled switch model
.MODEL Vswitch vswitch
+ (Ron = {(Vtm-0.7)/Itm}, Roff = {1.75E-3*Vdrm/Idrm},
+ Von = 5.0, Voff = 1.5)
* Diodes
.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL Dak D (Is=4E-11 Cjo=5pf)
* Allow the gate to float if required
Rfloat gate MT1 1e10
.ends

* R2 subcircuit
.subckt Potentiometer_R2 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* X1 subcircuit
.subckt VIR_LAMP_X1 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {220^2/100}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 300 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 220, {abs(V(port1, port2)) / 220}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 220}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

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Function

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Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Name diac triac

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Name

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RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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diac triac