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Signal |
Value |
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Signal |
Value |
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Cursor 1
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Cursor 2
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∆X
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1/∆X
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∆Y
|
∆Y (Phase)
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|---|---|---|---|---|---|
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| Out of date | |
| V | — |
| V | — |
| VPP | — |
| VRMS | — |
| VAV | — |
| fV | — |
| I | — |
| I | — |
| IPP | — |
| IRMS | — |
| IAV | — |
| fI | — |
| D | — |
| Out of date | |
| V | — |
| V | — |
| VPP | — |
| VRMS | — |
| VAV | — |
| fV | — |
| I | — |
| I | — |
| IPP | — |
| IRMS | — |
| IAV | — |
| fI | — |
| D | — |
| Out of date | |
| V | — |
| V | — |
| VPP | — |
| VRMS | — |
| VAV | — |
| fV | — |
| I | — |
| I | — |
| IPP | — |
| IRMS | — |
| IAV | — |
| fI | — |
| D | — |
| Out of date | |
| V | — |
| V | — |
| VPP | — |
| VRMS | — |
| VAV | — |
| fV | — |
| I | — |
| I | — |
| IPP | — |
| IRMS | — |
| IAV | — |
| fI | — |
| D | — |
| Out of date | |
| V | — |
| V | — |
| VPP | — |
| VRMS | — |
| VAV | — |
| fV | — |
| I | — |
| I | — |
| IPP | — |
| IRMS | — |
| IAV | — |
| fI | — |
| D | — |
| Out of date | |
| V | — |
| V | — |
| VPP | — |
| VRMS | — |
| VAV | — |
| fV | — |
| I | — |
| I | — |
| IPP | — |
| IRMS | — |
| IAV | — |
| fI | — |
| D | — |
ID:
ID:
View and edit circuit details below.
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Name
Name of saved file.
Description
Provides context to the design, and an explanation of the circuit operation. This is useful for highlighting theory or critical aspects of the design.
Type a string here. Matching tags appear as you type. Tap a matching tag, or enter a new tag.
This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.
Any error, warning or information messages appear below.
ID
Only one section is available for multisection components.
Rise time
s
With non-zero rise time, the signal converts to an analog signal from a digital signal.
Fall time
s
With non-zero fall time, the signal converts to an analog signal from a digital signal.
Use document settings
Mode
Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.
Output low
V
Maximum output voltage level to produce a low signal.
Input low threshold
V
Maximum input voltage level for the signal to be considered low.
Input high threshold
V
Minimum input voltage level for the signal to be considered high.
Output high
V
Minimum output voltage level to produce a high signal.
Show all symbol pin names
ID
Transient IC
V
DC NODESET
V
DC NODESET must be a number.
Net labels
ID
Select desired function.
Voltage reference
Voltage is the difference between the voltage probe and the Voltage reference selection.
Lists the probes using this probe as a negative reference.
Toggles direction of current measurement.
Use document settings
Mode
Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.
Output low
V
Maximum output voltage level to produce a low signal.
Input low threshold
V
Maximum input voltage level for the signal to be considered low.
Input high threshold
V
Minimum input voltage level for the signal to be considered high.
Output high
V
Minimum output voltage level to produce a high signal.
Enter an expression here. You can combine circuit variables with functions and operators to plot an expression in the Grapher.
Available variables for the expression.
Available functions, constants and operators for the expression.
Data origin.
Upload a data file here. You can view data from this file in the grapher.
Switch on to stream data from Source when simulation runs.
Plot
For data files with more than one plot, select the plot to view.
Application used to generate the Source data.
Type of simulation data in Source.
Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.
Instantaneous
Displays instantaneous measurements on probe during interactive simulation.
Periodic
Displays periodic measurements on probe during Interactive simulation.
Bias point(s)
Displays bias points on probe for DC Op simulation.
Show plots
Select to plot probe's data in Grapher.
Color
Select probe's trace color in Grapher.
Line weight
Select probe's trace thickness in Grapher.
Enable
Streaming works with Chrome only (on Windows or Android). Open Multisim Live in Chrome.
ID
Determines the conditions under which a waveform is first displayed on the Grapher. See Interactive simulation for more information.
Trace being triggered from. Available selections depend on placement and number of probes in schematic.
Edge of trace from selected Source that Grapher triggers from.
Point on Grapher y-axis that must be crossed by waveform before it displays.
Value must be a number.
Checkboxes toggle displayed values on and off.
Cursors are not displayed.
Displays a pair of cursors that can be dragged along the graph's x-axis.
Displays a pair of cursors that can be dragged along the graph's y-axis.
Displays a pair of x-axis cursors that, when dragged, move a corresponding pair of y-axis cursors to read specific data points.
The trace read by Cursor 1.
The trace read by Cursor 2.
Displays the x and y minimum and maximum for all data on the graph.
Scales the Magnitude axis so that its data fits the range of the graph window.
Scales the Phase (o) axis so that its data fits the range of the graph window.
Adjusts the time scale up/down.
Pinch or use the mouse wheel on the graph to zoom horizontally. Drag horizontally on the graph to pan.
Minimum
Lowest value on the x-axis.
Maximum
Highest value on the x-axis.
Pinch or use the mouse wheel on the Magnitude axis to zoom vertically. Drag vertically on the Magnitude axis to pan.
Vertical scale type.
Minimum
Lowest value on the Magnitude axis.
Maximum
Highest value on the Magnitude axis.
Pinch or use the mouse wheel on the Phase (o) axis to zoom vertically. Drag vertically on the Phase (o) axis to pan.
Minimum
Lowest value on the Phase (o) axis.
Maximum
Highest value on the Phase (o) axis.
Text
The simulation to run. See Simulation types for more information.
Name
Start time
s
End time
s
Manual time step
Time step
s
Manual time step
Time step
s
RELTOL
Relative error tolerance. A simulation wide accuracy control used to establish convergence.
VNTOL
V
Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.
ABSTOL
A
Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.
ITL1
DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.
ITL4
Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.
Method
Integration method. The numerical integration method used in transient analysis.
Temp
℃
Operating temperature. The temperature at which the entire circuit will be simulated.
Insert shunt resistance
Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.
RSHUNT
Ω
Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.
Use document settings
Mode
Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.
Output low
V
Maximum output voltage level to produce a low signal.
Input low threshold
V
Maximum input voltage level for the signal to be considered low.
Input high threshold
V
Minimum input voltage level for the signal to be considered high.
Output high
V
Minimum output voltage level to produce a high signal.
Width
Sheet width in grid squares.
Height
Sheet height in grid squares.
Grid
Toggles grid display.
Net Labels
Toggles all net labels.
Component Labels
Toggles all component labels.
View and edit circuit details below.
Select Public if you want your design to be viewable by all Multisim Live users.
Name
Name of saved file.
Description
Provides context to the design, and an explanation of the circuit operation. This is useful for highlighting theory or critical aspects of the design.
Type a string here. Matching tags appear as you type. Tap a matching tag, or enter a new tag.
I've changed the setting accordingly. Do not show this message again.
FPGA Board:
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
SW10
SW11
SW12
SW13
SW14
SW15
BTNU
BTND
BTNC
BTNL
BTNR
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
DP
AN0
AN1
AN2
AN3
JA0
JA1
JA2
JA3
JA4
JA5
JA6
JA7
JB0
JB1
JB2
JB3
JB4
JB5
JB6
JB7
JC0
JC1
JC2
JC3
JC4
JC5
JC6
JC7
JXADC0
JXADC1
JXADC2
JXADC3
JXADC4
JXADC5
JXADC6
JXADC7
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