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** EXP -10 (Binary To Gray) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: B0
aB0 1 Digital_Source_B0

* Component: B1
aB1 2 Digital_Source_B1

* Component: B2
aB2 3 Digital_Source_B2

* Component: B3
aB3 bridgeB3!OUT Digital_Source_B3

xbridgeB3!OUT bridgeB3!OUT 4 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U1
aU1 [2 1] bridgeU1!Y Digital_XOR2_U1

xbridgeU1!Y bridgeU1!Y 7 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U2
aU2 [3 2] bridgeU2!Y Digital_XOR2_U2

xbridgeU2!Y bridgeU2!Y 6 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U3
aU3 [bridgeU3!A 3] bridgeU3!Y Digital_XOR2_U3

xbridgeU3!A bridgeU3!A 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!Y bridgeU3!Y 5 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: X1
xX1 5 0 VIR_LAMP_X1

* Component: X2
xX2 6 0 VIR_LAMP_X2

* Component: X3
xX3 7 0 VIR_LAMP_X3

* Component: X4
xX4 4 0 VIR_LAMP_X4

* --- Circuit Models ---

* B0 model
.model Digital_Source_B0 d_constsource(State=1)

* B1 model
.model Digital_Source_B1 d_constsource(State=0)

* B2 model
.model Digital_Source_B2 d_constsource(State=0)

* B3 model
.model Digital_Source_B3 d_constsource(State=1)

* U1 model
.model Digital_XOR2_U1 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_XOR2_U2 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* U3 model
.model Digital_XOR2_U3 d_xor (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* X1 subcircuit
.subckt VIR_LAMP_X1 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {12^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 15 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 12, {abs(V(port1, port2)) / 12}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 12}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* X2 subcircuit
.subckt VIR_LAMP_X2 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {12^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 15 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 12, {abs(V(port1, port2)) / 12}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 12}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* X3 subcircuit
.subckt VIR_LAMP_X3 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {12^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 15 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 12, {abs(V(port1, port2)) / 12}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 12}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* X4 subcircuit
.subckt VIR_LAMP_X4 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {12^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 15 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 12, {abs(V(port1, port2)) / 12}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 12}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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RELTOL

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ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

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Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

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Minimum output voltage level to produce a high signal.

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EXP -10 (Binary To Gray)