Copy of Mini Projet of VLSI- Half adder

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Copy of Mini Projet of VLSI- Half adder

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A CMOS Half Adder circuit is the logic that uses more than one nMOS and one pMOS transistor(s). The nMOS(s) is used in Pull Down Network (PDN) and the pMOS(s) is used in Pull Up Network (PUN). Operation: When input is low, the nMOS is OFF and the pMOS is ON. Hence, the output is connected to VDD through pMOS.

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Creator

Sanjid18-3

72 Circuits

Date Created

3 years ago

Last Modified

3 years ago

Tags

  • Design of 2 input CMOS Adder

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