SR Latch reversible

Reversible SR NOR latch proposal (as mentioned in [1]). There was one limitation I came across while implementing this circuit diagram with the proposed logic gate that the S=0, R=0 hold condition was not accurate. Which is why I have proposed and additional SPDT(Single Pole Double Throw) switch with an inverted output to toggle towards the inverter side whenever we wish to hold the circuit in order to get accurate readings for Q and Q'. Kindly suggest any changes or mistakes if any, it would be greatly appreciated. Thanks 1.Hari, S.K.S., Shroff, S., Mahammad, S.N. and Kamakoti, V., 2006, August. Efficient building blocks for reversible sequential circuit design. In 2006 49th IEEE International Midwest Symposium on Circuits and Systems (Vol. 1, pp. 437-441). IEEE.