8 channel DAC
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Circuit Description
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The objective of this simulation is to confirm the impact of non-ideal resistors on the accuracy of the combined output and optimise the result for real resistor value.
Eight clock sources are used to step through all 256 possible levels at rates between 1 and 128Hz.
1) I intent to use ideal resistors to plot the output levels at each of the 256 steps. These will be output to a CSV file.
2) I will then change resistor values to those actually measured. Again a CSV file will be generated.
3) Repeat 2) for a different arrangement of resistors. I want to investigate a random resistor placement followed by three specific arrangements to determine which strategy results in the most accurate output.
4) The CSV files will be examined in Excel to determine the best RMS error fit to the ideal resistor situation before build commences.
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DMB says:
The first issues I noted were:
1) The saw-tooth nature of the time sweep. (I was expecting a descending staircase.)
2) The short pulses at the clock transition points.
The next most significant problem that I located was that the step size was larger (28.9mV) than predicted by calculation should be 19.5mV per step.
After adding voltage measurement points at the junctions of the 10K and 20K resistors and changing to a single 5VDC source connected through SPDT switches with the third port wired to ground. This enabled me to activate a single bit at a time and observe the effect on the output voltage along with each step in the R2R network.
This revealed that the voltage on both ends of R13 were identical. Further examination revealed that wire numbers on both sides of the resistor were both 9's effectively shorting out R13. Deleting and replacing all connections on both ends of R13 cured the saw-tooth problem resulting in a staircase with the correct step size but the transition pulses remained.
Along the way I adjusted the clocks for zero seconds rise and fall times as this should provide cleaner clock pulses.
Close examination of an exported CSV file revealed that at 0.5 seconds a pulse of 2.5V away from the ideal staircase (rising to 5V above ground when it should have been 2.5V.) The pulse duration was 2E-13 seconds! At each of the other transition points there were smaller spikes. I am 99.99% certain that this is the result of numerical (rounding) problems in the simulation engine.
From a practical point of view a 1pF capacitor from the output terminal to ground is sufficient to clear up the spikes in the staircase. In a real-world physical build on a breadboard typically there is ~4pF coupling between adjacent tracks so this is an appropriate correction. (ref. EEV blog somewhere.) Making this capacitor too large impacts on the rise time at t=0.
As mentioned earlier I will rebuild and re-post a properly working version.
Cheers David