LAB6

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LAB6

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The NMOS transistor has an input from Vss (ground) and PMOS transistor has an input from Vdd. The terminal Y is output. When a high voltage (~ Vdd) is given at input terminal of the inverter, the PMOS becomes open circuit and NMOS switched OFF so the output will be pulled down to Vss.

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LAB6 NAND

Maangchi

Creator

Maangchi

6 Circuits

Date Created

4 years, 1 month ago

Last Modified

4 years, 1 month ago

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