Copy of 8 channel DAC

The objective of this simulation is to confirm the impact of non-ideal resistors on the accuracy of the combined output and optimise the result for real resistor value. Eight clock sources are used to step through all 256 possible levels at rates between 1 and 128Hz. 1) I intent to use ideal resistors to plot the output levels at each of the 256 steps. These will be output to a CSV file. 2) I will then change resistor values to those actually measured. Again a CSV file will be generated. 3) Repeat 2) for a different arrangement of resistors. I want to investigate a random resistor placement followed by three specific arrangements to determine which strategy results in the most accurate output. 4) The CSV files will be examined in Excel to determine the best RMS error fit to the ideal resistor situation before build commences.