Dynamic CMOS logic half adder (1)

A CMOS Half Adder circuit is the logic that uses more than one nMOS and one pMOS transistor(s). The nMOS(s) is used in Pull Down Network (PDN) and the pMOS(s) is used in Pull Up Network (PUN). Operation: When input is low, the nMOS is OFF and the pMOS is ON. Hence, the output is connected to VDD through pMOS.