flip-flop Master-Slave D Latch (Edge-Triggered D Flip-Flop) cascade

This is a modification of the circuit Master-Slave D Latch (Edge-Triggered D Flip-Flop). All four two-input NAND gates of the D latch were replaced by three-input NAND gates and the two-input output NAND gates of the S-R latch were replaced by three-input NAND gates. This allows active-low Preset and Clear functions to be added to the circuit. When nPRESET is low an active-low SET is applied to the output S-R latch which forces Q high. At the same time this active-low SET is also applied to the input D latch so that it is kept set even if the clock stays low. When nCLEAR is low an active-low RESET is applied to the output S-R latch which forces Q low. At the same time this active-low RESET is also applied to the input D latch so that it is kept reset even if the clock stays low. Preset and Clear are asynchronous functions. Since nPRESET and nCLEAR are independent from CLK, they are also called DIRECT SET and DIRECT RESET.