CMOS Three-State Gate (Gated Output Driver)

The circuit is a three-state gate using n-channel and p-channel MOSFETs separately controlled by additional logic gates. The resistors are not part of the three-state gate, they are used to verify that the output goes to high-impedance state when the gate is disabled. When the control input (EN) is HIGH, both the NOR and NAND gates will invert the input signal (IN). If IN is LOW the n-channel MOSFET will be ON and the p-channel MOSFET is OFF, the output voltage will be close to ground potential. If IN is HIGH the n-channel MOSFET will be OFF and the p-channel MOSFET is ON, the output voltage will be close to power supply voltage. When the control input (EN) is LOW, regardless of the state of the input signal (IN), the output of the NOR gate is LOW and the output of the NAND gate is HIGH. Both MOSFETs are OFF, the output goes to high-impedance and the voltage at the output node is determined by the voltage divider formed by the supply voltage and the resistors. With the potentiometer wiper position at 50%, the output voltage should be 3.3 V ÷ 2 = 1.65 V. The circuit looks more complicated than the variant using series drivers. However, it occupies less area because the control gates conduct only small currents. The transistors making up the control gates will then have smaller geometries.