CMOS Buffered Inverter

Buffered CMOS Inverter using three cascaded inverter stages. An nMOS source follower is used between the output of the first stage and the output of the last stage. When the input is low and the output should go high, the nMOS source follower aids in current sourcing while the pMOS inverter of the last stage provides stronger voltage pull-up. Currently all devices are at 100 um. Dimensions and some other parameters should be modified to account for varying requirements (delay, voltage levels, current drive capability, symmetry/asymmetry of electrical properties) of each stage.