multiplier

The circuit implements a two-bit by two-bit multiplier by multiplying each bit of the multiplicand by each bit of the multiplier to form the partial products. The partial products are then weighted and summed to get the overall product. This is outlined in the diagram below: Mpcd1 Mpcd0 x Mplr1 Mplr0 ------------------------------------------------------------------- Mpcd1·Mplr0 Mpcd0·Mplr0 + Mpcd1·Mplr1 Mpcd0·Mplr1 ------------------------------------------------------------------- P3 P2 P1 P0 The diagram can be viewed correctly using fonts having fixed character widths, copying to a text editor is likely needed. Mpcd1 and Mpcd0 are the bits of the multiplicand. Mplr1 and Mplr0 are the bits of the multiplier. P3, P2, P1, and P0 are the bits of the product. P0 = Mpcd0·Mplr0, and it can be determined using only an AND gate. When Mpcd1·Mplr0 and Mpcd0·Mplr1 are added, a sum bit which becomes P1 and a carry bit C are generated. The carry bit C is then added to Mpcd1·Mplr1, the sum bit becomes P2 and the carry becomes P3. As shown in the circuit P1, P2, and P3 were obtained using two half-adders.