The circuit is a latched negative edge detector but the latch is a simple Set-Reset latch with active-high asynchronous set (PRESET). The output is active-low.
When PRESET is asserted the output of three-input NOR gate U2 and the main output ACTLOOUT are kept low and high, respectively. When PRESET is deasserted, ACTLOOUT will go low upon the arrival of the first high-going pulse from NOR gate U2. The output remains low until PRESET is asserted again.
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