Logic Circuit Equivalent Of 555 Timer Set-Reset Latch (NS LM555)

This circuit is equivalent to the circuit "555 Timer Set-Reset Latch" when the mode/configuration switch (Smode/Scfg) is open and the model used for the component 555 Timer behaves like National Semiconductor (NS) LM555. For Free Subscription version of Multisim Live, the only available model is IDEAL_TIMER which behaves like NS LM555. The circuit's input and output pins are: nRSTMCLR = Active low Master CLEAR, 555 Timer RESET input. THRESET = Active high RESET, 555 Timer THRESHOLD input. nTRSET = Active low SET, 555 Timer TRIGGER input. Qout = Latch push-pull output, 555 Timer main OUTPUT. Qdchg = Latch open-collector output, 555 Timer DISCHARGE output. Qout (555 Timer OUTPUT) is derived by complementing the output of the NAND gate using an inverter. Qdchg (555 Timer DISCHARGE) is derived by complementing the output of the NAND gate using a BJT inverter. Operation And Input Precedence: Master CLEAR nRSTMCLR is closest to the NAND gate and has the highest precedence. A logic LOW on this input, regardless of the states of THRESET and nTRSET, makes the output of the NAND gate high and the output of the inverter LOW. If nTRSET is HIGH (inactive) the output of the AND gate is high and the output of the NOR gate becomes LOW. If nTRSET remains HIGH the logic LOW output ot the NOR gate become stable and the output states of the NAND gate and the inverter will remain HIGH and LOW, resrectively, even if nRSTMCLR is returned HIGH (deasserted). A logic HIGH on THRESET, regardless of the state of nTRSET, makes the output of the NOR gate LOW which, similar to the action of nRSTMCLR will make the output states of the NAND gate and the inverter HIGH and LOW respectively. Farthest from the NAND gate input is nTRSET. A logic LOW on this input makes the output of the AND gate LOW. If THRESET is LOW (inactive) the output of the NOR gate will go HIGH, this tends to make the output of the NAND gate HIGH but only if nRSTMCLR is HIGH (inactive). If the output of the NAND gate goes LOW due to inactive nRSTMCLT and THRESET a logic LOW feedback goes to the other input of the AND gate. This logic LOW feedback keeps the output of the NAND gate LOW even when nTRSET is deasserted as long as nRSTMCLR and THRESET also remain inactive. Consequently the NAND gate output is maintained LOW and the output of the inverter HIGH. A voltage probe is placed on Qdchg but its logic state simply follows that of Qout. As stated above, THRESET has precedence over nTRSET, if the two input sources are asserted simultaneously THRESET overrides nTRSET (the output resets). This is the behavior of National Semiconductor's LM555. In contrast, for Signetic's NE555 and most other manufacturer's version of the 555 Timer, nTRSET has higher priority than THRESET. Signetics NE555 (et. al.)'s behavior is not available in Free Subscription version of Multisim Live.