3 Bit Synchronous up Counter on 14 th

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3 Bit Synchronous up Counter on 14 th

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This 4-bit digital counter is a sequential circuit that uses JK flipflops, AND gates, and a digital clock. For each clock tick, the 4-bit output increments by one. After it reaches it's maximum value of 15 (calculated by 2^4-1), it resets to zero. Each probe measures one bit of the output, with PR1 measuring the least significant bit and PR4 measuring the most significant bit. PR5 is the clock. Expand this circuit by adding a digital to analog converter!

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3 Bit Synchronous up Counter on 14 th

puviarasu11

Creator

Yogasundari

71 Circuits

Date Created

4 years ago

Last Modified

4 years ago

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