Browser not supported

✕
Go back

Tier limit reached

✕

sr astabile (1)

0
Favorite
1
copy
Copy
454
Views
Open Circuit
sr astabile (1)
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for sr astabile (1)

Circuit Graph

D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

There are currently no comments

Profile image for Roberto_Petrucci

sr astabile (1) (1)

Roberto_Petrucci

Creator

Profile image for roberto_petrucci

Roberto_Petrucci

10 Circuits

Date Created

4 years, 7 months ago

Last Modified

4 years, 7 months ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From

sr astabile

Related Circuits

Preview of 4-Bit Digital Counter

4-Bit Digital Counter

by Dayna

29273
16
copy
921
Preview of 3 bit Counter

3 bit Counter

by KWen99

16429
4
copy
160
Preview of Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

by GGoodwin

9459
0
copy
31

© 2024 National Instruments Corp. ALL RIGHTS RESERVED.

Hosted Services Terms Privacy Policy Export Notices Terms of Use

Circuit Graph

✕
Graph image for sr astabile (1)

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕