P-channel JFET Proper Bias Test Circuit 1.0

P-channel and N-channel JFETs conduct hole or electron current, respectively, from the Source to the Drain. The JFET symbol has the gate drawn on the Source side of the symbol. (Note the gate at the top of the JFET symbol, and the direction of the gate arrow, indicating P-channel and N-gate.) Here, the PJFET is biased with +3.3Vdc, and the gate voltage, Vg, is adjusted with the pot. The drain-source voltage that causes the current limiting condition at Vg=0 is called the “pinch-off” voltage (Vp). This basic circuit can be used to test for pinch-off, and to see the effect of varying Vg with varying Vds (drain-to-source voltage). This circuit can be used to sweep Vds to plot pinch-off voltage.