MUX 2*1

The circuit switches the two input data A and B for transmission to the output. When the data select (S) input is 0, the upper AND gate is masked, its output is 0 regardless of the logic state of B. The lower AND gate, on the other hand, will follow the logic state of A. Therefore B is blocked while A is allowed to be transmitted. When S is 1, A is blocked while B is transmitted.