Half Adder (STLD)

0
Favorite
0
copy
Copy
341
Views
Half Adder (STLD)

Circuit Description

Graph image for Half Adder (STLD)

Circuit Graph

The circuit performs the function of adding two binary digits. Using its two input bits the circuit produces the sum and the carry bits as its output signals. The SUM output bit will be set if either but not both of the input bits is 1. The CARRY output bit will be set if both of the input bits are 1. A two-input XOR gate and a two-input AND gate were used for the SUM and CARRY outputs respectively.

There are currently no comments

Creator

shrijee

18 Circuits

Date Created

4 years ago

Last Modified

4 years ago

Tags

  • adder
  • carry
  • sum
  • half-adder
  • half adder

Circuit Copied From