D flip-flop from NAND gates Lab 07

0
Favorite
10
copy
Copy
1638
Views
D flip-flop from NAND gates Lab 07

Circuit Description

Graph image for D flip-flop from NAND gates Lab 07

Circuit Graph

D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

There are currently no comments

Profile image for Muvva2021

D flip-flop by Using NAND gates

Muvva2021
Profile image for DKRABARI

D flip-flop from NAND gates Lab 07

DKRABARI
Profile image for RA1911030010077

rahul kamal ra1911030010077 (1)

RA1911030010077
Profile image for Rupa9375

D flip-flop from NAND gates Lab 07

Rupa9375
Profile image for Salman2255

D flip-flop from NAND gates Lab 07

Salman2255
Profile image for joejohnny27

D flip-flop

joejohnny27
Profile image for prateekbanik.ece

D flip-flop using NAND gate

prateekbanik.ece
Profile image for vinay99

D flip-flop from NAND gates

vinay99
Profile image for kowshik2003

D flip-flop from NAND gates

kowshik2003
Profile image for user-28397

D flip-flop from NAND gates Lab 07

user-28397

Creator

DavidFahs-Brown

7 Circuits

Date Created

4 years, 11 months ago

Last Modified

4 years, 11 months ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From