Coincidence Gate Clock/Frequency Doubler

The circuit generates an output square wave having a frequency twice that of the input square wave. This is done through an RC delay circuit and a coincidence gate. Complementary output signals are generated by using both Exclusive OR (XOR) and Exclusive NOR (XNOR) gates. The outer terminals of the gates are feed directly with the input clock/square wave signal. The input signal also goes to the delay circuit through the resistor. The inner terminals of the gates are connected to the junction of the RC delay circuit. At the edges (transition from HIGH to LOW and vice versa) of the input clock, due to the presence of the RC circuit, the voltage at the inner terminals of the gates cannot quickly follow the voltage at the outer terminals. Initially then the input terminals of both gates are at opposite logic levels. The XOR gate will produce a logic HIGH output while the XNOR gate will produce a logic LOW. As the capacitor charges following a LOW to HIGH transition, or discharges following a HIGH to LOW transition, the voltage at the inner terminals will rise or fall towards the voltage at the outer terminals. As the rising/falling voltage is recognized to be at the same logic level as the state of the outer terminals, the XOR and XNOR gates will change state. By proper choice of the resistance and capacitance values, the delay can be adjusted so that the output signals are practically symmetrical (≈50% duty cycle). Ideally the alternation of logic state at the output of the gates should happen at every transition of the input signal which results to doubling of the output frequency. However, as the capacitor is initially fully discharged, the alternation will happen irregularly until the DC level of the capacitor voltage rises halfway of low and high threshold levels of the gates.