15.12

This circuit is a variant of majority voting logic circuit which determines whether the majority of the input signals are logic 1s or logic 0s. If the majority of the input signals consist of 1s the output is set to logic 1 otherwise it will be at logic 0. Since the number of input variables in this circuit is even, the result of voting could be a tie. This particular circuit breaks a tie by favoring logic 1. The circuit then simply checks if any two combination of the input signals are all 1s. This is done by using six two-input AND gates with the outputs applied to a six-input OR gate.