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3 To 8 Decoder / 1 Of 8 Decoder/Demultiplexer

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Circuit Description

The circuit is 3 To 8 Decoder / 1 Of 8 Decoder/Demultiplexer with active low output. The inverters provide the complements of the input signals nG0, C, B, and A. Three of the five input terminals of NAND gates connect either to C, B, A or to their complements. The remaining two input terminals of NAND gates connect to G1 and the output of nG0 inverter. G1 is an active high ENABLE or multiplexed inverting data input. nG0 is an active low ENABLE or multiplexed noninverting data input.

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