JK Flip-flop

0
Favorite
4
copy
Copy
191
Views
JK Flip-flop

Circuit Description

Graph image for JK Flip-flop

Circuit Graph

This 4-bit digital counter is a sequential circuit that uses JK flipflops, AND gates, and a digital clock. For each clock tick, the 4-bit output increments by one. After it reaches it's maximum value of 15 (calculated by 2^4-1), it resets to zero. Each probe measures one bit of the output, with PR1 measuring the least significant bit and PR4 measuring the most significant bit. PR5 is the clock. Expand this circuit by adding a digital to analog converter!

There are currently no comments

Profile image for eiffel_mtz

Copy of JK Flip-flop

eiffel_mtz
Profile image for eiffel_mtz

Copy of JK Flip-flop

eiffel_mtz
Profile image for eiffel_mtz

JK Flip-flop_VF

eiffel_mtz
Profile image for eiffel_mtz

Copy of JK Flip-flop_VFYa

eiffel_mtz

Creator

eiffel_mtz

105 Circuits

Date Created

2 years, 3 months ago

Last Modified

2 years, 3 months ago

Tags

  • digital
  • counter
  • 4-bit

Circuit Copied From