Browser not supported

✕
Go back

Tier limit reached

✕

Exam_2_EC

0
Favorite
0
copy
Copy
115
Views
Open Circuit
Exam_2_EC
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for Exam_2_EC

Circuit Graph

D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

There are currently no comments

Creator

Profile image for rabiskar123

rabiskar123

4 Circuits

Date Created

5 months ago

Last Modified

5 months ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From

D flip-flop

Related Circuits

Preview of 4-Bit Digital Counter

4-Bit Digital Counter

by Dayna

28970
17
copy
920
Preview of 3 bit Counter

3 bit Counter

by KWen99

16332
4
copy
160
Preview of Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

by GGoodwin

9357
0
copy
31

© 2024 National Instruments Corp. ALL RIGHTS RESERVED.

Hosted Services Terms Privacy Policy Export Notices Terms of Use

Circuit Graph

✕
Graph image for Exam_2_EC

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕