J-K Latch

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J-K Latch

Circuit Description

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This is a J-K latch with active high Enable (C), the functions are tabulated below: NO CHANGE: J=0, K=0 RESET: J=0, K=1 SET: J=1, K=0 With J and K both high: when C is high, Q and NOTQ will be both high which is invalid when C is low, Q and NOTQ will be at equal logic states cycling HIGH and LOW fast

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GGoodwin

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Creator

GGoodwin

1116 Circuits

Date Created

6 years, 3 months ago

Last Modified

2 years, 8 months ago

Tags

  • flip-flop
  • jk latch
  • j-k
  • j-k latch
  • jk
  • jk flip-flop
  • j-k flip-flop
  • latch
  • jk flip flop
  • j-k flip flop