d sanju148

This is a combination of the D Latch??? and Set-Reset (S-R/RS) Latch With Enable which are both improvements to NAND Set-Reset (S-R/RS) Latch. When the enable input (C) is high the D input can control the Q and NOTQ output just as in the D Latch???. When C is low D is inhibited from controlling the output of the latch, Q and NOTQ simply retain their previous states.