J-K Latch
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Circuit Description
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This is a J-K latch with active high Enable (C), the functions are tabulated below:
NO CHANGE: J=0, K=0
RESET: J=0, K=1
SET: J=1, K=0
With J and K both high:
when C is high, Q and NOTQ will be both high which is invalid
when C is low, Q and NOTQ will be at equal logic states cycling HIGH and LOW fast
Creator
Prajwall8
15 Circuits
Date Created
2 years, 8 months ago
Last Modified
2 years, 8 months ago
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