cella di memoria

This is a combination of the modifications made in the circuits "NOR Reset-Set (RS/R-S/SR/S-R) Latch With Enable" and "D Latch???" which are both variations of the circuit "NOR Reset-Set (RS/R-S/SR/S-R) Latch". When the enable input (nC) is low the D input can control the Q and NOTQ output (Q follows D and NOTQ is the complement of D) just as in the D Latch. When nC is high D is inhibited from controlling the output of the latch, Q and NOTQ simply retain their previous states.