Ayush 19/IT/12 D Flip-Flop (1)

This circuit is an interconnection of D and S-R latches in master-slave configuration. This results to a negative-edge-triggered D flip-flop. This can be converted to a positive-edge-triggered flip-flop by inserting an inverter at the clock (CLK) input. The output signals always start in undetermined state but this will be removed by the subsequent falling edge of the clock (CLK) input where the state of the D input and its complement replace Q and NOTQ respectively.