Single-Supply (5 V) Model Of 555 Timer

The circuit is a model of the 555 Timer IC. This is useful when studying the 555 at the comparator and logic gate level. Currently the model is limited to +5V single-supply operation. The analog interface to TRIGGER and THRESHOLD input terminals is modeled using ideal comparators U1 and U2. The reference levels are obtained using three 5 kΩ resistors working as a two-tap voltage divider to yield Vcc/3 and 2·Vcc/3 for TRIGGER and THRESHOLD comparators respectively. The three 5 kΩ resistors are used in bipolar 555 Timer ICs which led to the myth that the numeric designation 555 is from these resistors. CMOS 555s use much higher values for the three resistanceS to attain a minimal quiescent current. Texas Instruments' TLC551 and TLC555, in particular, use a MOSFET active divider to generate the reference levels. The set-reset latch is created using NAND gates U5 and U6. U5 has three input terminals to accommodate the RESET function. For simplicity, another analog comparator with a 700 mV reference is used for RESET interface. 555 Timer ICs come in many variants, which are not exactly identical. Of particular importance is the behavior of the THRESHOLD and TRIGGER when asserted simultaneously. In 555, race condition is avoided because these two input sources are given precedence. However, manufacturers assigned precedence to these input terminals differently. Signetics, who introduced the 555 timer to the market in the form of NE555/SE555, gave priority to the TRIGGER input. This is the norm followed by other manufacturers such as EXAR (XR-555), HARRIS (CA555/LM555), MOTOROLA (MC1455/MC1555), RAYTHEON (RC555/RM555), RCA (CA555), SGS-Thomson (NE555/SA555/SE555), and many more. On the other hand, National Semiconductor produced their LM555 as a functional equivalent of NE555/SE555 but with THRESHOLD having higher priority than TRIGGER. This model takes this discrepancy into account and allows the circuit to be configured into any of these two modes through switch Scfg. When Scfg is straight (|), the lower input of NAND gate U4 is connected to Vcc and the model behaves like National Semiconductor's LM555. When Scfg is slant (\), the lower input of NAND gate U4 is connected to the output of inverter U8 and the model behaves like Signetics' NE555/SE555. The 555 Timer component available in Free Subscription version of Multisim Live behaves like National Semiconductor's LM555. Inverter U8 can be deleted if (connections to) input terminals of trigger comparator U1 are swapped. Wiring the TRIGGER comparator with the reference connected to the noninverting input and the external trigger input signal connected to the inverting input is customary. Preference is then given to this somewhat standard practice to avoid confusion to the user when referring to other sources of information. Inverter U7 can also be deleted if OUTPUT (push-pull output) is obtained from the output of NAND gate U6 instead. The current form of the output section of the model is a closer approximation to the actual circuit however.