RTL LOGIC NAND GATE

CMOS NAND GATE: let us give logic 1, P-MOS Transistor will be turned off and N-MOS transistor will be turned on. If we logic 0, P-MOS transistor will be turned on and N-MOS transistor will be turned off. In C-MOS NAND logic, both P-MOS transistors are connected in parallel and both N-MOS transistors are connected in series. Input of 1st P-MOS transistor will be connected to input of 1st N-M0S transistor. similarly, input of 2nd P-MOS transistor is connected to input of 2nd N-MOS transistor. when we give logic 0 to both of inputs A and B, both P-MOS transistors will be turned on and both N-MOS transistors will be turned off. when we give logic 0 to one input and logic 1 to one input, the logic 0 will turns off P-MOS transistor and turns on N-MOS transistor. similarly logic 1 will turns off P-MOS transistor and turns on N-MOS transistor. when we give logic 1 to both of the inputs, both P-MOS transistors will be turned on and both N-MOS transistors will be turned on.