Browser not supported

✕
Go back

Tier limit reached

✕

Tirth 628 exp 10 UP (JK - FF& Clock)

0
Favorite
3
copy
Copy
281
Views
Open Circuit
Tirth 628 exp 10 UP (JK - FF& Clock)
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for Tirth 628 exp 10 UP (JK - FF& Clock)

Circuit Graph

Synchronous Counter Design a 3-bit synchronous counter with the sequence below by using JK flip flops. 1 5  3  7  4 0 2  6  ... Apply the clock pulses and observe the output. Verify your design with output waveform simulation

There are currently no comments

Profile image for RA1911003010578

exp 10 UP (JK - FF& Clock)

RA1911003010578
Profile image for Tanya546

546 exp 10 UP

Tanya546
Profile image for Ayush_568

ayush exp 10

Ayush_568

Creator

Profile image for ra191100301628

RA191100301628

22 Circuits

Date Created

4 years, 2 months ago

Last Modified

4 years, 2 months ago

Tags

  • digital
  • counter

Circuit Copied From

exp 10B (JK - FF& Clock)

Related Circuits

Preview of D flip-flop

D flip-flop

by Sobrjery

11761
7
copy
270
Preview of 3-bit Adder

3-bit Adder

by EESal

6475
2
copy
25
Preview of 3-Bit Asynchronous Counter Using D-Flip Flop

3-Bit Asynchronous Counter Using D-Flip Flop

by Angeles_Maila

6373
1
copy
22

© 2024 National Instruments Corp. ALL RIGHTS RESERVED.

Hosted Services Terms Privacy Policy Export Notices Terms of Use

Circuit Graph

✕
Graph image for Tirth 628 exp 10 UP (JK - FF& Clock)

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕