RA1911028010081 - Experiment 10 (Down Counter)
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Synchronous Counter
Design a 3-bit synchronous down counter with the sequence below by using JK flip flops.
1 5 3 7 4 0 2 6 ...
Apply the clock pulses and observe the output.
Verify your design with output waveform simulation
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RA1911028010081
20 Circuits
Date Created
4 years, 2 months ago
Last Modified
4 years, 2 months ago
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