(Gated) D Latch
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This is a combination of D Latch??? and Set-Reset (S-R/RS) Latch With Enable which are both improvements to NAND Set-Reset (S-R/RS) Latch. Refer to my circuits "D Latch???", "Set-Reset (S-R/RS) Latch With Enable", and "NAND Set-Reset (S-R/RS) Latch".
When enable input (C) is high the D input can control Q and NOTQ just as in the circuit D Latch???. When C is low D is inhibited from controlling the output of the latch, Q and NOTQ simply retain their previous states.
Private Copy
Private Copy
Creator
GGoodwin
1116 Circuits
Date Created
6 years, 3 months ago
Last Modified
3 years, 1 month ago
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