Configurable-Precedence NAND S-R Latch
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This is an enhancement to the circuit NAND Set-Reset Latch With Precedence. Three more additional two-input NAND gates were added to make the precedence between SET and RESET easily selectable.
The two input signals remain both active-high, a third input (PRCTL) controls the precedence/priority between SET and RESET. If PRCTL is 1 SET has precedence over RESET, if PRCTL is 0 RESET has precedence over SET.
Creator
Leonardo-ACADÊMICO
48 Circuits
Date Created
3 years, 3 months ago
Last Modified
3 years, 3 months ago
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