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Set-Reset (S-R/RS) Latch With Enable

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Circuit Description

This is a modification of NAND Set-Reset (S-R/RS) Latch, refer to my circuit "NAND Set-Reset (S-R/RS) Latch", two additional NAND gates were used so that the circuit now includes an ENABLE function. When enable input (C) is high the S and R input can control Q and NOTQ output just as in the circuit NAND Set-Reset (S-R/RS) Latch. When C is low S and R are inhibited from controlling the output of the latch, Q and NOTQ simply retain their previous states.

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sr Latch With Enable

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Clocked S-R Latch

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Testing

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