Testing

This is a modification of the NAND Set-Reset (S-R/RS) Latch, two additional NAND gates were used so that the circuit now includes an ENABLE function. When the enable input (C) is high the S and R input can control the Q and NOTQ output just as in the NAND Set-Reset (S-R/RS) Latch. When C is low S and R are inhibited from controlling the output of the latch, Q and NOTQ simply retain their previous states.