Exercis 5.1

A differential stage with passive load is designed. A gain of 40 dB should be reached with a DC output voltage of 0:9V. The input common mode voltage is 0:9V. The transistor M3 and M4 have the same sizes. The channel length modulation is neglected and the current at the current source Isrc is 2 μA. Vdd = 1:8V Technology Parameters: 65nm-Technology, kn = 200 μA=V2, kp = 50 μA=V2,  = 0:2V􀀀1, Vth = 0:5V a) Calculate the resistance R. b) Calculate the DC voltage Vs c) Calculate W L ratio of transistor M1 and M2. d) Explain what happen with the dc parameter if the channel length modulation is not zero. e) Calculate the gain of the differential stage (now with output resistance).