A 24 KWINAL DLD

The circuit performs the two-input Exclusive OR (XOR) logic function using three-level NAND gates. When the input signals are both logic LOW, NAND gates U2 and U3 both generate logic HIGH so the final output goes LOW. When the input signals are both logic HIGH, the output of NAND gate U1 becomes LOW resulting to NAND gates U2 and U3 both generating logic HIGH so the final output goes LOW. When the input signals are different, the output of NAND gate U1 is logic HIGH, NAND gates U2 and U3 will go to different logic states so the final output goes HIGH.