synchronous counter that goes through states 2 , 4 , 6 , 7 , 0 , 2 using J K flip flop

0
Favorite
1
copy
Copy
929
Views
synchronous counter that goes through states 2 , 4 , 6 , 7 , 0 , 2 using J K flip flop

Circuit Description

Graph image for synchronous counter that goes through states 2 , 4 , 6 , 7 , 0 , 2 using J K flip flop

Circuit Graph

This 4-bit digital counter is a sequential circuit that uses JK flipflops, AND gates, and a digital clock. For each clock tick, the 4-bit output increments by one. After it reaches it's maximum value of 15 (calculated by 2^4-1), it resets to zero. Each probe measures one bit of the output, with PR1 measuring the least significant bit and PR4 measuring the most significant bit. PR5 is the clock. Expand this circuit by adding a digital to analog converter!

There are currently no comments

Profile image for kiprop-dave

synchronous counter that goes through states 2 , 4 , 6 , 7 , 0 , 2 using J K flip flop

kiprop-dave

Creator

Riya70

172 Circuits

Date Created

3 years, 1 month ago

Last Modified

3 years, 1 month ago

Tags

This circuit has no tags currently.

Circuit Copied From