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sr astabile (1) (1)

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D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

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sr astabile (1) (1) (1)

Roberto_Petrucci

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Roberto_Petrucci

10 Circuits

Date Created

4 years, 7 months ago

Last Modified

4 years, 7 months ago

Tags

  • digital
  • nand gate
  • flip-flop

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sr astabile (1)

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