RA2111003011401 UP

Synchronous Counter Design a 3-bit synchronous counter with the sequence below by using JK flip flops. 1 5  3  7  4 0 2  6  ... Apply the clock pulses and observe the output. Verify your design with output waveform simulation k map Ja=1 Ka=1 Jb=Qa Kb=Qa Jc= Qa Qb ; Kc=Qa Qb 0x 0x1x