Cmos nand

CMOS NAND GATE: We know that when 0v(logic 0) is given as input to pmos transistor it is ON. when 5v(logic 1) is given as input to the pmos transistor it is OFF. when 0v(logic 0) is given as input to nmos transistor it is OFF. when 5v(logic 1) is given as input to the nmos transistor it is ON. We place two nmos transistors N1 and N2 in parallel and two pmos transistors P1 and P2 connected in series and the input of N1 transitor is connected to input of P1 transistor And input of N2 transistor is connected to input of P2 transistor in cmos nand gate. when we take input as Logic low (logic 0) both pmos transistors are ON and both nmos transitors are OFF the current doestnot reaches ground then we get output volatge as logic high(logic 1). when we take input as Logic high (logic 1) both pmos transistors are OFF and both nmos transitors are ON the current reaches ground then we get output volatge as logic low(logic 0). when we take input as logic low and logic high P1 transitor and N2 transistor is ON and P2 transistor and N1 transistor is OFF then we get output as logic 0 because output reaches ground from N2 transistor,and same happens when we take input has logic high and logic low . By this we get output as cmos NAND gate.