NOR R-S Latch With Precedence

This is an enhancement to the circuit NOR Reset-Set (RS/R-S/SR/S-R) Latch. One additional NOR gate and one inverter were added to allow the circuit to give priority to one input over the other. This resolves the contention when the two input signals are simultaneously asserted and keeps Q and NOTQ always at complementary logic states. In this particular configuration the two input signals are both active-low and nRESET has precedence over nSET. When nRESET is high the output of the inverter is low, NOR gate U3 is recessive and NOR gate U2 simply acts as inverter to the nSET input. If nSET is asserted the output of NOR gate U2 will be high which sets the latch (NOTQ = 0, Q = 1). When nRESET is asserted (low) the output of the inverter is high which makes the output of NOR gate U3 low. At the same time the output of NOR gate U2 is also low, regardless of the state of nSET input, which makes NOR gate U4 recessive. Thus, the latch is reset (Q = 0, NOTQ = 1).