RS FLIP FLOP (1)

This circuit consists of two S-R latches in master-slave configuration. The interconnection results to a pulse-triggered flip-flop. The triggering pulse is applied to the S or R input (but not simultaneously) while C is high. At the start of simulation the output signals will be in undetermined state. This condition can be exited by setting C high (if it is initially low), S and R at opposing logic state (if S and R are both set to 1, the undetermined state will persist and this cannot be exited), then setting C back to low. Fewer initialization steps will be needed with C high, S and R at opposing states at the start of simulation. After initialization the latch/flip-flop will function as tabulated below: SET: S=1, R=0; S is pulsed high while enable (C) is active (1) RESET: S=0, R=1; R is pulsed high while enable (C) is active (1) NO CHANGE: S=0, R=0 If both S and R are set to 1 while C is active, Q and NOTQ are undefined. The pulse at S and R sets or resets the first latch, the output of this latch is transferred to the second latch when enable (C) is returned low.