Down Counter

0
Favorite
2
copy
Copy
144
Views
Down Counter

Circuit Description

Graph image for Down Counter

Circuit Graph

Synchronous Counter Design a 3-bit synchronous counter with the sequence below by using JK flip flops. 1 5  3  7  4 0 2  6  ... Apply the clock pulses and observe the output. Verify your design with output waveform simulation

There are currently no comments

Profile image for ds3140@srmist.edu.in

Down Counter 749

ds3140@srmist.edu.in
Profile image for Devansh02

Down Counter 719

Devansh02

Creator

Yuvraj02

17 Circuits

Date Created

2 years, 11 months ago

Last Modified

2 years, 11 months ago

Tags

  • digital
  • counter

Circuit Copied From