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SIPO SHIFT REGISTER 3-BIT (1)

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SIPO SHIFT REGISTER 3-BIT (1)
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D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

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PIPO SHIFT REGISTER 3-BIT

Chaitanya942
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Copy of SIPO SHIFT REGISTER 3-BIT (1)

user-1442422
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Copy of SIPO SHIFT REGISTER 3-BIT (1)

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Chaitanya942

24 Circuits

Date Created

4 years ago

Last Modified

4 years ago

Tags

  • digital
  • nand gate
  • flip-flop

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SISO SHIFT REGISTER 3-BIT

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